EX-184B uP, 2xEthernet, PHY, USB, CAN, RTOS & TCP/IP SW – Grid Connect
USB 3.0 SSIC PHY IP Core
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Physical layer - Wikiwand
MB86C311A TQFP-64 chip with hardware AES USB 3.0 PHY (Device) USB 3.0 IC | eBay
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
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USB2 PHY | Cadence
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Mixed-Signal Verification for USB 2.0 Physical Layer IP
HSIC USB 2.0 PHY IP
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Electronics | Free Full-Text | Ethernet Packet to USB Data Transfer Bridge ASIC with Modbus Transmission Control Protocol Based on FPGA Development Kit
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High Speed Inter-CHIP USB 2.0 PHY | Arasan Chip Systems
TPS65982 USB Type-C & Power Delivery Controller - TI | Mouser
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
PHY (circuito integrado) - Wikipedia, la enciclopedia libre
USB 2.0 Full High Speed Solution | NXP Semiconductors
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
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USB 2.0 extender control chipCH317 - NanjingQinhengMicroelectronics
USB 2.0 PHY IP Core Device Host OTG Hub in TSMC, 28HPC, 40LP /LL, UMC, 40LP, 28HPC, SMIC 14SF, SF, 55LL, 40LL - T2M-IP
![USB3300 Transceiver: Features, Pinout, and Datasheet [Video&FAQ]](https://res.utmel.com/Images/UEditor/72083c43-5731-4f70-b870-d0c7fd2bebce.jpg "USB3300 Transceiver: Features, Pinout, and Datasheet [Video&FAQ]")